The present invention relates to integrated circuit memory devices and more particularly, to memory devices having buffered write circuits and methods of operation thereof.
FIG. 1 is a block diagram showing a conventional synchronous-type static random access memory (SRAM) having a late write function. A synchronous-type SRAM is described in Korean Laid-Open Patent Application No. 2002-0074993.
Referring to FIG. 1, the SRAM device includes a data input register 12. The data input register 12 latches burst data and transfers the latched data to a write circuit 14 in response to control signals from a control circuit 10. The write circuit 14 receives the burst data from the data input register 12 and writes the received burst data into a memory cell array 16. A read circuit 18 reads the burst data from the memory cell array 16 and outputs the read burst data to an external device through an output buffer 20. In addition, the output buffer 20 outputs the latched data in the data input register 12 in case of a bypass read operation mode. The data input register 12 receives data from an external device and latches the received data in response to data input control signals DIN_CON_i_H. The latched data is output to the write circuit 14 in response to a flag signal Cell_Sel_H.
In the bypass read operation mode, the data is output from the data input register 12, not from the memory cell array 16, i.e., “bypassing” the memory cell array 16. The semiconductor memory device having the late write function as shown in FIG. 1 temporarily stores the data in the data input register 12 (i.e., a buffer cell) when a first write command is generated, and stores the data stored in the buffer cell into the memory cell array 16 when a second write command is generated. If the data is read before the data is stored in the memory cell array 16 (namely, before the next write command is generated), the data temporarily stored in the buffer cell is output to the external device. This operation is called a buffer read operation. A network DRAM applied to network equipment may also have a late write function.
In the above-described conventional semiconductor memory device, the data output path from the memory cell array 16 may be different from the path when the data is output from the buffer cell 12. That is, the data output from the memory cell array 16 may be amplified in an I/O sense amplifier and then is output to the external device, but the data output from the buffer cell 12 is output to the external device without passing through the I/O sense amplifier in the buffer read operation. Thus, if the data is output from the buffer cell, a reordering circuit may be required to reorder the output order of the data output from the buffer cell 12. If a reordering circuit is added to the semiconductor memory device so as to execute the buffer read operation, the number of tri-state buffers additionally required may be increased in proportion to the number of data output pins. In addition, additional wires for the semiconductor memory device may be required. As a result, chip size may increase and design cost for the chip may increase.